By Topic

A programmable data background generator for march based memory testing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Wei-Lun Wang ; Dept. of Electron. Eng., Cheng Shiu Inst. of Technol., Kaohsiung, Taiwan ; Kuen-Jong Lee

Due to the short test time and high fault coverage, march algorithms have been widely used to test the SRAM and DRAM memory chips and cores in a system-on-chip (SOC). To raise the fault coverage of the word-oriented memories (WOMs), distinct data backgrounds of the march algorithms are required. In this paper we have integrated two kinds of data background generators into a single design in the built-in self-test (BIST) environment. The proposed data background generator can generate different sizes and different kinds of data backgrounds for testing the WOMs. It is shown that the design is easily programmable with very little external control. Also when combined with the existing data register in the memory, the hardware overhead is quite small.

Published in:

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Date of Conference: