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Automatic Verilog code generation of an 8-bit RISC micro-controller

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3 Author(s)
Yun-Tai Husueh ; Southern Taiwan Univ. of Technol., Tainan, Taiwan ; Wen-Chung Chang ; Jui-Min Lai

In this paper, we describe a design method, which can automatically generate Verilog code for an 8-bit RISC microcontroller with a user-defined instruction set. With this method, one can shorten the development time, increase the efficiency of Verilog coding, and decrease the man-hour requirement. Most of all, even those who do not have the knowledge and techniques of a Verilog coding for a RISC microcontroller are able to design a microcontroller through this method. First of all, classify the instruction set of the microcontroller to be designed, into file register and literal operation, bit file register operation, control operation, and branch operation. Then provide four stage pipeline (fetch, decode, execute and write) control signals for the microcontroller. Finally, use C/C++ language to generate the Verilog code. Finally some manually fine tune of the design is still required during pre/post simulation of the Verilog code.

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ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

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