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Real-time segmentation architecture of gray-scale/color motion pictures and digital test-chip implementation

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4 Author(s)
Morimoto, T. ; Res. Center for Nanodevices & Syst., Hiroshima Univ., Higashi-Hiroshima, Japan ; Harada, Y. ; Koide, T. ; Mattausch, H.J.

This paper proposes a digital algorithm for gray-scale/color image segmentation of real-time video signals and a cell-network-based implementation architecture in state-of-the-art CMOS technology. Through extrapolation of test-chip-data design in 0.35 μm CMOS technology and simulation results we predict that about 50,000 ∼ 100,000 pixels can be integrated on a chip in a 0.09 μm CMOS technology, realizing very high-speed segmentation at about 300 μsec per gray-scale/color image. Consequently real-time color-video segmentation will become possible in near future.

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ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

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