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A track-and-hold circuit using a tail current source dividing technique

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3 Author(s)
Suzuki, K. ; Dept. of Commun. & Integrated Syst., Tokyo Inst. of Technol., Japan ; Fujii, N. ; Takagi, S.

This paper proposes a tail current source dividing technique for increasing precision of a track-and-hold circuit without reducing the sample speed. The proposed technique is based on division of a tail current source into two current sources during a hold period to reduce signal errors caused by parasitic capacitance coupling between the input and output terminals. With the proposed technique, a SFDR of 62 dB for 25 MHz, 1 Vp-p input signal at 200 MS/s is achieved with 0.35 μm CMOS parameters by HSPICE simulation.

Published in:

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Date of Conference:

2002