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A high-throughput low-cost AES cipher chip

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4 Author(s)
Tsung-Fu Lin ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chih-Pin Su ; Chih-Tsun Huang ; Cheng-Wen Wu

We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 μm CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5 K gates.

Published in:

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

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