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A novel self-repairable parallel multiplier architecture, design and test

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3 Author(s)
Rong Lin ; Comput. Sci., State Univ. of New York, NY, USA ; Margala, M. ; Kazakova, N.

A novel, self-repairable, parallel multiplier architecture with high speed low power CMOS parallel counter circuits and design-for-test (DFT) implementations is presented. The illustrated 16×16-b multiplier architecture can be easily reconfigured into 17 different architectures for fault recovering. Also described is a novel verification scheme that performs exhaustive data validation. Compared to previous parallel multiplier architectures, the proposed multiplier architecture has reduced transistor count, enhances yield using built-in self-repair mechanism and provides high performance at low-voltages. The proposed exhaustive DFT technique greatly reduces the test vector length required to verify the data validity, from 17*232 vectors needed in a conventional architecture to only 1.3*213 vectors needed in this architecture. Furthermore, the concepts presented are scalable to larger multiplier architectures.

Published in:

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

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