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A model-based methodology for application specific energy efficient data path design using FPGAs

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4 Author(s)
Mohanty, S. ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Seonil Choi ; Jang, Ju-wook ; Prasanna, V.K.

Presents a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration (DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection. We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area.

Published in:

Application-Specific Systems, Architectures and Processors, 2002. Proceedings. The IEEE International Conference on

Date of Conference:

2002

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