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Fast and compact error correcting scheme for reliable multilevel flash memories

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3 Author(s)
Rossi, D. ; Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy ; Metra, C. ; Ricco, B.

This paper presents a method to reduce area and timing overhead due to the implementation of standard single symbol correcting codes to provide multilevel (ML) flash memories with error correction ability. In particular the proposed method is based on the manipulation of the parity check matrix which defines a code, which allows us to minimize the matrix weight and the maximum row weight. Furthermore, we show that a minimal increase in the redundancy, with respect to the standard case, allows a further considerable reduction of the impact on the memory access time, as well as on the area overhead due to the error correction circuitry.

Published in:

On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International

Date of Conference:

2002