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A system level approach in designing dual-duplex fault tolerant embedded systems

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4 Author(s)
C. Bolchini ; Dipt. di Elettronica e Inf., Politecnico di Milano, Italy ; L. Pomante ; F. Salice ; D. Sciuto

This paper presents an approach for designing embedded systems able to tolerate hardware faults, defined as an evolution of our previous work proposing an hardware/software co-design framework for realizing reliable embedded systems. The framework is extended to support the designer in achieving embedded systems with fault tolerant properties minimizing overheads and limiting power consumption. A reference system architecture is proposed; the specific hardware/software implementation and reliability methodologies (to achieve the fault tolerance properties) are the result of an enhanced hw/sw partitioning process driven by the designer' constraints and by the reliability constraints, set at the beginning of the design process. By introducing also the reliability constraints during specification, the final system can benefit from the introduced redundancy also for performance gains, while limiting area, time, performance and power consumption overheads.

Published in:

On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International

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