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In this paper the results of a series of intrinsic hardware evolution experiments with a CMOS FPTA chip are presented. The experiments discussed are restricted to the evolution of specified target DC behaviors. In the first series of experiments the evolution of different logic gates, namely NAND, NOR, AND, OR and XOR, is studied. The success rates in evolving the different logic gates are compared to each other Furthermore the influence of three different methods of presenting the test patterns to the chip is analyzed In a second series of experiments the evolution of a Gaussian voltage transfer characteristic is tackled. Thereby the influence of the chip area available to the genetic algorithm is studied.