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Modern System-on-Chip (SoC) designs are steadily increasing in complexity, while verification strategies, based on traditional logic simulations, are becoming extraordinarily and intolerably slow. On the other side, rapid system prototyping frameworks are not yet scalable and modular enough to prototype complex multi-processor systems. The proposed solution offers a modular approach for the validation of SoCs containing up to 128 heterogeneous processors. The RSP framework is based on a multi-board PCI architecture. An inter-task, layered data synchronization protocol has been implemented in order to ease HW-SW partitioning, co-design and design space exploration.