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In this paper, we present an efficient methodology to functionally verify high performance algorithms using a Hardware/Software Prototype based on reconfigurable hardware attached to a standard PC We start from a conceptual design on system level using the commercial Cadence Cierto VCC tool, by defining the system in several behavioral blocks, each of them having the functionality described in standard C or C++. This software-only system is then refined by selecting certain blocks to be implemented in hardware, which are then described in Handel-C, then compiled and mapped to Xilinx Virtex FPGAs. The hardware blocks are seamlessly integrated into the VCC environment by stub modules, which perform the hardware/software interfacing and communication via shared memory DMA transfers. This paper presents the methodology and illustrates it using an example of a Viterbi encoder/decoder.