By Topic

Modeling gate oxide short defects in CMOS minimum transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Renovell, M. ; Lab. d''Informatique Robotique Microelectronique de Montpellier, Univ. Montpellier II, France ; Galliere, J.M. ; Azais, F. ; Bertrand, Y.

In this paper a new model is proposed for gate oxide short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows us to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in detail using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.

Published in:

Test Workshop, 2002. Proceedings. The Seventh IEEE European

Date of Conference:

2002