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Modeling gate oxide short defects in CMOS minimum transistors

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4 Author(s)
Renovell, M. ; Lab. d''Informatique Robotique Microelectronique de Montpellier, Univ. Montpellier II, France ; Galliere, J.M. ; Azais, F. ; Bertrand, Y.

In this paper a new model is proposed for gate oxide short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows us to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in detail using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.

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Test Workshop, 2002. Proceedings. The Seventh IEEE European

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