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A hierarchical colored hardware Petri net (HCHPN) based model was proposed in (A. K. Murugavel et al, Proc. of Intl. Conf. on VLSI Design, pp. 181-186, 2001) for estimating switching activity in combinational circuits. In this paper, we model sequential circuits as HCHPNs incorporating real delays for both gates and interconnects. Thus, the given sequential circuit is first modeled as a HCHPN and simulated for switching activity estimation in the Petri net domain which leads to better accuracy and faster simulation. Experimental results for ISCAS'89 benchmark circuits show that the proposed HCHPN model yields accuracy on an average within 4.4% of that of PowerMill. The per-pattern simulation time for HCHPNs is about 2.4 times less than that of PowerMill.