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A power and resolution adaptive flash analog-to-digital converter

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4 Author(s)
Jincheol Yoo ; Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA ; Daegyu Lee ; Kyusun Choi ; Jongsoo Kim

A new power and resolution adaptive flash ADC, named PRA-ADC, is proposed. The PRA-ADC enables exponential power reduction with linear resolution reduction. Unused parallel voltage comparators are switched to standby mode. The voltage comparators consume only the leakage power during the standby mode. The PRA-ADC, capable of operating at 5-bit, 6-bit, 7-bit, and 8-bit precision, dissipates 69 mW at 5-bit and 435 mW at 8-bit. The PRA-ADC was designed and simulated with 0.18 μm CMOS technology. The PRA-ADC design is applicable to RF portable communication devices, allowing tighter management of power and efficiency.

Published in:

Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on

Date of Conference:

2002