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An adaptive serial-parallel CAM architecture for low-power cache blocks

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2 Author(s)
Efthymiou, A. ; Dept. of Comput. Sci., Manchester Univ., UK ; Garside, J.D.

There is an on-going debate about which consumes less energy: a RAM-tagged associative cache with an intelligent order of accessing its tags and ways (e.g. way prediction), or a CAM-tagged high associativity cache. If a CAM search can consume less than twice the energy of reading a tag RAM, it would probably be the preferred option for low-power applications. Based on memory traces - which usually cause tag mismatch within the lower four bits - a new serial CAM organisation is proposed which consumes just 45% more than a single tag RAM read and is only 25% slower than the conventional, parallel CAM. Furthermore, it can optionally be operated as a parallel CAM, at no speed penalty, and still reduce energy consumption.

Published in:

Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on

Date of Conference:

2002