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An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model

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3 Author(s)
Sunghyun Lee ; EECS, Seoul Nat. Univ., South Korea ; Sungjoo Yoo ; Kiyoung Choi

This paper presents a method of intra-task dynamic voltage scaling (DVS) for SoC design with hierarchical FSM and synchronous dataflow model (in short, HFSM-SDF model). To have an optimal intra-task DVS, exact execution paths need to be determined in compile time or runtime. In general programs, since determining exact execution paths in compile time or runtime is not possible, existing methods assume worst/average-case execution paths and take static voltage scaling approaches. In our work, we exploit a property of HFSM-SDF model to calculate exact execution paths in runtime. With the information of exact execution paths, our DVS method can calculate exact remaining workload. The exact workload enables to calculate optimal voltage level which gives optimal energy consumption while satisfying the given timing constraint. Experiments show the effectiveness of the presented method in low-power design of an MPEG4 decoder system.

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Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on

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