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Graph-based quantum integrated circuits using III-V mulch-branch nanowire networks and their nano-Schottky gate control

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5 Author(s)
Kasai, S. ; Res. Center for Integrated Quantum Electron., Hokkaido Univ., Sapporo, Japan ; Yumoto, M. ; Fukushi, T. ; Muranaka, T.
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Beyond the scaling limit of Si CMOS LSls, one envisages nanoelectronics based on quantum devices. To realize quantum LSls (Q-LSIs), however, a novel architecture is required that is suitable to non-robust and charge-sensitive quantum devices which manipulate a single or a few electrons. The cascaded logic gate architecture in Si LSIs is utterly unsuitable. The purpose of this paper is to propose a graph-based Q-LSI architecture and to investigate its basic feasibility by forming of high-density GaAs-based and InP-based multi-branch nanowire networks and controlling them by nanometer-scale Schottky gates.

Published in:

Device Research Conference, 2002. 60th DRC. Conference Digest

Date of Conference:

24-26 June 2002