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A reconfigurable data-flow architecture for a class of image processing applications

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3 Author(s)
Sinha, A. ; R&D Center, Himachal Futuristic Commun. Ltd., Gurgaon, India ; Neogi, S. ; Maiti, K.

This paper aims to device an architecture which uses the capability of asynchronous concurrency of the data flow architecture as well as spatial parallelism of SIMD machines for a class of image processing applications using reconfigurable processing elements (RPE). Overall processing speed is enhanced by: (a) concurrent functioning of the RPE; and (b) replacing software execution of signal processing functions by hardware approach using FPGA as RPE. Thus, a hybrid architecture, which functions as a data flow machine at a functional level and exploits the capability of spatial parallelism by incorporating modified SIMD concepts is presented.

Published in:

Circuits and Systems for Communications, 2002. Proceedings. ICCSC '02. 1st IEEE International Conference on

Date of Conference:

2002

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