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Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga/sub 2/O/sub 3/ gate oxide, an undoped Al/sub 0.75/Ga/sub 0.25/As spacer layer, and undoped In/sub 0.2/Ga/sub 0.8/As as channel layer. The p-channel devices with a gate length of 0.6 /spl mu/m exhibit a maximum DC transconductance g/sub m/ of 51 mS/mm which is an improvement of more than two orders of magnitude over previously reported results. With the demonstration of a complete process flow and 66% of theoretical performance, GaAs MOS technology has moved into the realm of reality.
Date of Publication: Sept. 2002