Referenced Items are not available for this document.
Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga/sub 2/O/sub 3/ gate oxide, an undoped Al/sub 0.75/Ga/sub 0.25/As spacer layer, and undoped In/sub 0.2/Ga/sub 0.8/As as channel layer. The p-channel devices with a gate length of 0.6 /spl mu/m exhibit a maximum DC transconductance g/sub m/ of 51 mS/mm which is an improvement of more than two orders of magnitude over previously reported results. With the demonstration of a complete process flow and 66% of theoretical performance, GaAs MOS technology has moved into the realm of reality.
Published in:
Electron Device Letters, IEEE
(Volume:23
,
Issue:
9
)
Date of Publication: Sept. 2002
- Page(s):
- 508 - 510
- ISSN :
- 0741-3106
- INSPEC Accession Number:
- 7377266
- Digital Object Identifier :
- 10.1109/LED.2002.802591
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 07 November 2002
- Issue Date :
- Sept. 2002
- Sponsored by :
- IEEE Electron Devices Society
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