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Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET

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2 Author(s)
Kumar, M.J. ; Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India ; Verma, V.

For the first time, we report the combined application of a SiGe source and a delta-doped p+ region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transistor latch when compared to the conventional SOI MOSFET thus improving the reliability of these structures in VLSI applications

Published in:

Reliability, IEEE Transactions on  (Volume:51 ,  Issue: 3 )

Date of Publication:

Sep 2002

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