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Table look-up model of thin-film transistors for circuit simulation using spline interpolation with transformation by y=x+log(x)

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3 Author(s)
Kimura, M. ; Technol. Platform Res. Center, Seiko Epson Corp., Nagano, Japan ; Inoue, S. ; Shimoda, T.

A table look-up model of thin-film transistors has been developed for circuit simulation. This model utilizes three schemes. First, the spline interpolation with transformation by y = x+log(x) achieves precision for both on-current and off-current simultaneously. Second, the square polynomial supplement solves an anomaly near the points where drain voltage equals zero. Third, the linear extrapolation achieves continuities of the current and its derivatives as a function of voltages for areas outside where the spline interpolation is performed and improves convergence during circuit simulation

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:21 ,  Issue: 9 )

Date of Publication:

Sep 2002

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