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A parallel/pipelined VLSI architecture designed to maximize concurrency and throughput is described for real-time hyperspectral image classification. To obtain a real-time architecture, we first simplified the constrained linear discriminant analysis (CLDA) algorithm and its computation flow. Next, we folded and modified its structure to reduce data dependency, to increase pipelining, and to minimize the silicon area. The required and yet slow data whitening process was avoided by using a modified target classifier, it is shown that applying the modified target classifier to the original data is equivalent to applying the original target classifier to the whitened data. Additionally, a high performance iterative matrix inversion algorithm simplifies the circuit complexity and improves processing time for repetitive matrix inversions and updates. Finally, to manage the high volume of data, an internal numerical representation is used. Additionally, a multiplexed bus reduces the I/O pins by sharing input data pins with pins to download registers with their initial values.