By Topic

Extraction of parallel hardware during C to VHDL translation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jie Chen ; Dept. of Electr. & Comput. Eng., Tennessee Technol. Univ., Cookeville, TN, USA ; Haggard, R.L.

Translating C/C++ language into VHDL is an important step in synthesizing hardware from C/C++. However, there is no explicit facility in the general C/C++ language to declare concurrent parallel execution which is a critical characteristic of hardware systems. This paper presents the outline of a set of transformation algorithms. These algorithms are helpful in the process of extracting parallel hardware during C to VHDL translation. An example of extracting parallel hardware from an array addition routine written in C is also presented in this paper.

Published in:

System Theory, 2002. Proceedings of the Thirty-Fourth Southeastern Symposium on

Date of Conference: