Design issues for digital control of boost power factor correction converters

There has been much interest in power factor correction (PFC). For reasons of price, the control algorithms for single-phase PFC converters are in most cases implemented as analog circuits. For the near future, as the price/performance ratio of DSP's is expected to decrease further, there is a fair chance that the analog control circuits will be abandoned in favor of digital implementations. This paper deals with specific problems encountered when full digital control is applied to the boost PFC converter. The different control loops are discussed, while special attention is being paid to sampling and to the timing in the processor. All theoretical results are verified by experiments on a 1 kW/50 kHz prototype.