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A novel approach is introduced that exploits characteristics of fixed-point, two's complement data in order to reduce power consumption related to switching activity. This approach is based on an intuitive switching activity model that captures the most essential data characteristics with statistical parameters. The approach is embodied in a heuristic that uses the model to systematically reduce switching activity of interconnect between data path units. The perspective provided by the model and heuristic allows efficient and intuitive high-level design space exploration. This approach is demonstrated through an example of high-level design space exploration for a low power processor dedicated to implementing the IS-54 vector-sum excited linear predictive (VSELP) speech codec. Application of the heuristic results in up to 56% activity reduction at high energy locations in the data path and estimated processor power reduction of about 15% on average during encoding compared to an obvious implementation.