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A 6 K GaAs gate array with fully functional LSI personalization

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13 Author(s)
Peczalski, A. ; Honeywell Syst. & Res. Center, Minneapolis, MN, USA ; Lee, G. ; Betten, W.R. ; Somal, H.
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A 12×12 multiplier consisting of 19000 devices was successfully implemented on a 6000-gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160°C range. The backgating and dynamic (switching) noise are also discussed as the key noise-margin limiting factors. A specialized on-chip circuitry which enables on-chip measurement and fault localization in complex GaAs ICs is proposed and implemented. The high yield of the multiplier (10%) seems to be limited only by particle contamination, which indicates that the noise margin is satisfactory for the GaAs nonselfaligned depletion-mode fabrication process

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Solid-State Circuits, IEEE Journal of  (Volume:23 ,  Issue: 2 )