By Topic

Automatic reconfiguration and yield of the TESH multicomputer network

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Maziarz, B.M. ; SKF Condition Monitoring, San Diego, CA, USA ; Jain, V.K.

This paper considers defect tolerance issues for parallel computing systems based on a new interconnection network, namely "Tori connected mESHes (TESH)". Key features of this network are the following: it is hierarchical, thus allowing exploitation of computation locality and systematic expansion up to a million processors; and it appears to be well-suited for VLSI/ULSI realization, including 3D implementation. The goal here is to present efficient reconfiguration algorithms for such hierarchical parallel computing systems. Despite the dramatic improvement in defect density in recent years, it is still necessary to provide redundancy and defect circumvention to achieve acceptable system-level yields for large multicomputer systems. The TESH-based parallel systems are no exception. Therefore, we develop placement and routing algorithms that assign logical nodes to healthy physical nodes and configure switches to bypass the defective cells, switches and links. Simulations indicate that the placement is nearly 100 percent effective, while the routing performance diminishes with increasing defect density for a given extent of redundancy. The approach scales up well because, in TESH networks, essentially the same kind of sparing is used at all levels.

Published in:

Computers, IEEE Transactions on  (Volume:51 ,  Issue: 8 )