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Challenges in the design high-speed clock and data recovery circuits

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1 Author(s)
Razavi, B. ; California Univ., Los Angeles, CA, USA

This article describes the challenges in the design of monolithic clock and data recovery circuits used in high-speed transceivers. Following an overview of general issues, the task of phase detection for random data is addressed. Next, Hogge (1985), Alexander (1975), and half-rate phase detectors are introduced and their trade-offs outlined. Finally, a number of clock and data recovery architectures are presented.

Published in:

Communications Magazine, IEEE  (Volume:40 ,  Issue: 8 )