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Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments

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5 Author(s)
S. Rzepka ; Dept. of Electr. Eng., Dresden Univ. of Technol., Germany ; E. Hofer ; E. Simon ; E. Meusel
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A design assessment and optimization process for wafer-level chip size packages (WLCSP) is demonstrated. Besides the basic design, the thermal stress in WLCSPs with underfill and with increased standoff height, respectively, are analyzed by finite element method (FEM) simulations. The results are validated and a lifetime model is calibrated by experiments. Also, a WLCSP with stacked balls is optimized using the FEM models. Its total gain in lifetime over the basic design is estimated to reach 780%. WLCSP with optimum underfill endure 10 to 20 times longer than the basic WLCSPs. Soft underfill, however, has almost no effect on the critical inelastic strain. In addition to these practical results, the paper discusses some of the risks of FEM models (such as the singularity problem) and proposes ways of avoiding or overcoming them.

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IEEE Transactions on Electronics Packaging Manufacturing  (Volume:25 ,  Issue: 2 )