By Topic

N-channel 3C-SiC MOSFETs on silicon substrate

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Jianwei Wan ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Capano, M.A. ; Melloch, M.R. ; Cooper, J.A., Jr.

Inversion-mode, n-channel 3C-SiC MOSFETs have been fabricated in a 3C-SiC epilayer grown on a 2°-off-axis Si(001) substrate with optimized SiC processing techniques. Phosphorus implantations are employed for source/drain formation and a sheet resistance of 70 Ω per square is obtained after annealing at 1250°C for 30 min in argon. Both drain characteristics and subthreshold characteristics show typical transistor behavior with an effective channel mobility of 165 cm2/Vs. The breakdown field of the gate oxide is about 3.5 MV/cm.

Published in:

Electron Device Letters, IEEE  (Volume:23 ,  Issue: 8 )