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Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology

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3 Author(s)
Chan, S.C. ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA ; Shepard, Kenneth L. ; Dae-Jin Kim

This paper extends transistor-level static noise analysis to consider the unique features of partially depleted silicon-on-insulator (PD-SOI) technology: floating-body-induced threshold voltage variations and parasitic bipolar leakage currents. This involves a unique state-diagram abstraction of the device physics determining the body potential of PD-SOI FETs. Based on this picture, a simple model of the body voltage is derived which takes into account modest knowledge of which nets have dependable regular switching activity. Results are presented using a commercial static noise analysis tool incorporating these extensions and comparisons are made with SPICE.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:21 ,  Issue: 8 )