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A simple all MOS continuous-time multiplier/divider cell and its applications in VLSI signal processing

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2 Author(s)
Khachab, N.I. ; Solid-State Lab., Ohio State Univ., Columbus, OH, USA ; Ismail, M.

A novel, simple, all-MOS continuous-time multiplier/divider parameterized cell is presented. The cell uses only four MOS depletion FETs and two operational amplifiers (op-amps) or one fully balanced output op-amp. The resulting circuit is fully integrable in MOS technology. The cell is highly reconfigurable, versatile, extremely simple to design, and its output is conveniently programmed via DC control voltages. Some of the applications of the cell in analog VLSI signal processing include analog multiplication, signal squaring, division, signal inversion, amplitude modulation, RMS-to-DC conversion, and sensor linearization. Moreover, the new circuit is easily extendible to achieve analog vector multiplication, and hence lends itself naturally to the analog MOS VLSI implementation of feedback/feedforward neural networks

Published in:

Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on

Date of Conference:

14-16 Aug 1989