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Numerically controlled oscillators (NCOs), with a hybrid scheme of both look-up tables (LUT) and coordinate transformation digital computer (CORDIC) algorithms for a hardware efficient, high performance sine/cosine function generation are investigated. This scheme combines fast access and power efficiency of reasonably sized LUTs, and arbitrary precision obtainable from a rigorous iteration algorithm. Systematic studies using hardware description language (HDL) models and synthesis lead to optimum LUT/CORDIC ratios, which minimize power consumption and silicon area for a given operating clock frequency. First order error models are presented as guidelines for choosing internal NCO parameters. The NCO accuracy is tested with HDL simulations for all algorithmic states to limit output errors to 1 least significant bit (LSB) and by spectra derived from discrete Fourier transform (DFT) for typical frequency inputs f, resulting in a signal to noise ratio (SNR) of better than 100 dB for an amplitude word length AW of 16 bit. Two benchmark designs were adopted for the two clock frequencies 200 MHz and 20 MHz, as "high" and "moderate" performance, respectively. The NCO models are synthesized in a 0.35 /spl mu/m CMOS standard cell target technology and optimized to actually achieve after layout maximum clock frequencies exceeding 310 MHz, i.e., signal frequencies of up to 100 MHz.