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The authors discuss the design, development and implementation of the 9-kb (256-word×37-bit) associative memory used in the single-chip array processing element (SCAPE) chip, a CMOS VLSI associative parallel processor (APP) that integrates 256 associative processing elements (APEs) on a single 68-pad chip to achieve high-speed, cost-effective image and signal processing. It is shown that a static CMOS content-addressable memory (CAM) design is unsuited to the constraints of the SCAPE chip architecture and that a purely nMOS CAM cell provides the best compromise between the conflicting area, speed, power, and control requirements. Comprehensive details of this design are given together with an evaluation of its performance. Finally, a description of the design methodology used in the construction of the SCAPE chip is presented with a breakdown of circuit areas and operational data
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:23
,
Issue:
2
)
Date of Publication: Apr 1988
- Page(s):
- 543 - 548
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 3190692
- Digital Object Identifier :
- 10.1109/4.1020
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Apr 1988
- Sponsored by :
- IEEE Solid-State Circuits Society
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