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CMOS amplifier design with enhanced slew rate and power supply rejection

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2 Author(s)
Lee, B.W. ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Sheu, B.J.

The performance of several types of analog VLSI circuits is limited by the settling behavior and power supply rejection of CMOS amplifiers. Three novel techniques in MOS amplifier design, including nonsaturated input differential pair, improved cascode structure, and biasing circuitry, are described. A two-stage amplifier using these techniques has been fabricated in the MOSIS scalable 2-μm CMOS technology, and achieves 80-V/μs slew rate and 57-dB power-supply rejection ratio (PSRR) at 50 kHz with DC power dissipation of 1 mW

Published in:

Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on

Date of Conference:

14-16 Aug 1989

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