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A novel algorithm for automated optimum design of IIR SC decimators

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3 Author(s)
Ngai, P.C. ; Dept. of Electr. & Electron. Eng., Univ. of Macau, China ; Martins, R.P. ; Franca, J.E.

This brief presents a novel algorithm for optimizing the design of infinite-impulse response (IIR) switched-capacitor (SC) decimators. It is implemented with a computer-assisted iterative methodology to achieve minimum capacitance spread and usually leading also to the minimization of the total capacitor area, while considering scaling for maximum signal handling capability. A linear/nonlinear programming method is adopted for optimum adjustment of the capacitance values, within a specific decimator structure and a finite number of iterations. Several examples of automatic and optimum design of second-order IIR SC decimators are presented, together with a comparison against previous designs, obtained for the same circuits through the use of traditional methods

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:49 ,  Issue: 4 )