By Topic

Enumeration of test sequences in increasing chronological order to improve the levels of compaction achieved by vector omission

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Pomeranz, I. ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Reddy, S.M.

We describe a method to improve the levels of compaction achievable by static compaction procedures based on vector omission. Such procedures are used to reduce the lengths of test sequences for synchronous sequential circuits without reducing the fault coverage. The proposed procedure enumerates, in increasing chronological order, test sequences consisting of subsets of the vectors included in a given test sequence that needs to be compacted. The unique feature of this approach is that test vectors omitted from the test sequence at an earlier iteration can be reintroduced at a later iteration. This results in a less greedy procedure and helps reduce the compacted test sequence length beyond the length that can be achieved if vectors are omitted permanently as in earlier procedures

Published in:

Computers, IEEE Transactions on  (Volume:51 ,  Issue: 7 )