By Topic

A low power high performance distributed DCT architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)

A new distributed arithmetic architecture, NEDA, is presented in this paper. NEDA is a low power optimized architecture based on the distributed arithmetic paradigm. In addition to low power performance, NEDA offers high speed and reduced area. In NEDA, inner product computational module has been proved, mathematically, to require only additions. Moreover, minimum number of additions is used by exploiting the redundancy in the adder array. Such properties have made a NEDA unit a basic computational module for high performance DSP architectures. A case study of 8×8 DCT NEDA-based architecture is analyzed. Savings exceeding 88% are achieved for the DCT implementation

Published in:

VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on

Date of Conference:

2002