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A MOS approach to CMOS DET flip-flop design

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4 Author(s)
Varma, P. ; IBM India Res. Lab., Indian Inst. of Technol., New Delhi, India ; Panwar, B.S. ; Chakraborty, A. ; Kapoor, D.

A novel approach to double-edge-triggered (DET) flip-flop design is presented along with a new static flip-flop and a new dynamic flipflop. The approach builds CMOS circuits using pass transistors and MOS-style clocked inverters and addresses issues of threshold voltage drop (VT drop) and circuit complexity. Among DET designs, the number of switched and total transistors used by our flip-flops is less than or equal to any in related work. Our circuits beat all others in speed (maximum frequency response) by significant margins at medium to high supply voltages. The speed outperformance range for our static flip-flop is 1.5 to 5 V and for our dynamic flip-flop is <2.5 to 5 V

Published in:

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:49 ,  Issue: 7 )

Date of Publication:

Jul 2002

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