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A high performance complementary bipolar process using PBSOI technique

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7 Author(s)
Kim, J.H. ; Process R & D Group, Fairchild Korea Semicond., Kyonggi-Do, South Korea ; Lee, S.H. ; Lee, K.H. ; Park, H.J.
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In this paper, for the first time, we suggest a novel high voltage, high speed and latch-up free NPN transistor and PNP transistor fabrication technology using PBSOI (Patterned and Bonded Silicon On Insulator) and STI (Shallow Trench Isolation) technology. Using this technique, we can easily control the breakdown voltage (BVceo) without the problem of P+B/L out-diffusion. In this PBSOI process, after diffusion of well (collector), the Buried Layer is diffused on the well. In addition, unlike the prior technology that devices are fabricated in epitaxial layer, the proposed devices are formed in active wafer itself, therefore we can get defect-free devices promising excellent characteristics. The peak fTs for NPN and PNP transistor are 10 GHz and 9 GHz, the values of BVceo for the NPN and PNP devices are 15 V and 17 V, respectively. Finally, these values were found to be excellent results as shown in the maximum value of Johnson-limit for the fT-BVceo product.

Published in:

Power Semiconductor Devices and ICs, 2002. Proceedings of the 14th International Symposium on

Date of Conference:

2002