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A novel bit line technology for self-aligned storage node contact has been developed to overcome the issues related with downscaling of COB stack DRAM cells for the 90 nm DRAM technology node and beyond. In this new scheme, both ILD gap fill tolerance and SAC etching selectivity of SiO/sub 2/ to Si/sub 3/N/sub 4/ are significantly enhanced because there is no need to form Si/sub 3/N/sub 4/ spacer around the bit-line and because of the better profile of top mask Si/sub 3/N/sub 4/. Furthermore, compared to the conventional scheme, the novel bit line has the advantages of device performance such as refresh time and speed because the parasitic bit line capacitance is decreased by as much as 25%. The new bit line technology has been developed and verified with a 0.12 /spl mu/m 512 Mb DRAM product. The results obtained from a 0.12 /spl mu/m DRAM technology confirm that this novel bit line scheme is beneficial for the 90 nm technology node and beyond.