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High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors

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11 Author(s)
I. Kudo ; ULSI Device Dev. Div., NEC Corp., Kanagawa, Japan ; S. Miyake ; T. Syo ; S. Maruyama
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We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body-slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.

Published in:

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Date of Conference:

11-13 June 2002