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In this report, a high performance silicon-on-insulator (SOI) transistor for the 100 nm CMOS technology node is presented. Partially depleted (PD) transistors were fabricated in a 1000 /spl Aring/-thick silicon film with gate lengths down to 45 nm, using a 16 /spl Aring/ nitrided gate oxide. At an operating voltage of 1.2 V, self-heated drive currents of 940 /spl mu/A//spl mu/m and 460 /spl mu/A//spl mu/m were achieved at 20 nA//spl mu/m for NMOS and PMOS respectively. Floating body effects (FBE) were minimized by special diode junction engineering to achieve maximum overall performance. A measured median stage delay of 6 ps was achieved on an inverter-fan-out-1 ring oscillator at 1.3 V at a total N+P leakage of 30 nA//spl mu/m. The exceptional AC performance of this technology is among the highest reported in the literature at this low transistor leakage and operating voltage.
Date of Conference: 11-13 June 2002