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60 nm gate length dual-Vt CMOS for high performance applications

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30 Author(s)
M. Mehrotra ; Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA ; J. Wu ; A. Jain ; T. Laaksonen
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In this work, we present a 60 nm gate length CMOS for high performance applications at the 0.13 /spl mu/m CMOS node. The technology utilizes 193 nm gate lithography, dual spacers with thin spacer before drain extension implant and L-shaped nitride spacer after drain extensions, and remote-plasma nitrided dielectric with 1.75 nm EOT. 10-15% improvement in drive current is achieved with lower series resistance by reduction of dopant loss and higher dopant activation, resulting in n- and pMOS I/sub drive/ of 1160 /spl mu/A//spl mu/m and 550 /spl mu/A//spl mu/m at 1.3 V at I/sub off/=100 nA//spl mu/m.

Published in:

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Date of Conference:

11-13 June 2002