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A 100 nm CMOS technology with "sidewall-notched" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications

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27 Author(s)
Nakai, S. ; Fujitsu Labs. Ltd., Tokyo, Japan ; Takao, Y. ; Otsuka, S. ; Sugiyama, K.
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A 40 nm CMOS transistor, an ultra high density 6T SRAM cell, and 10-level Cu interconnects and very-low-k (VLK) dielectrics for high performance microprocessor applications are presented. Key process features are the following: (1) High-NA 193 nm photolithography with phase shift mask and optical proximity correction (OPC) allows 40 nm gate length and the smallest 6T SRAM cell (<1 /spl mu/m/sup 2/). (2) A unique transistor feature which is referred to as "sidewall-notched gate" enables an optimal pocket implant placement and suppresses variations of the notch width much better than poly-notched gate structure. (3) 1.1 nm nitrided oxide (1.9 nm inversion T/sub ox/) is used to achieve high drive current, and the thermal budget is reduced to suppress the boron penetration. (4) SiC-capped Cu/SiLK structure in 0.28 /spl mu/m pitch metal 1-4 layers realizes k/sub eff/ of 3.0.

Published in:

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Date of Conference:

11-13 June 2002