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High soft-error tolerance body-tied SOI technology with partial trench isolation (PTI) for next generation devices

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11 Author(s)
Y. Hirano ; ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan ; T. Iwamatsu ; K. Shiga ; K. Nii
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It was proven that the body-tied SOI technology with partial trench isolation (PTI) has significant high soft-error immunity. As compared with the bulk, a three-order reduction of the soft-error rate for a 0.18 /spl mu/m SOI 4 Mbit SRAM with the PTI was successfully realized by the balanced combination of the SOI thickness and well resistance. It is estimated that the soft-error immunity for the floating-body device degrades because large charge collection is induced by not only the body strike but also the drain strike. A design guideline of the SOI structure to suppress soft errors is presented. According to the guideline, beyond 0.13 /spl mu/m node, high soft-error immunity for the body-tied SOI device was projected as compared with the bulk as well as the body-floating SOI device.

Published in:

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Date of Conference:

11-13 June 2002