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Soft error rate scaling for emerging SOI technology options

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9 Author(s)
P. Oldiges ; IBM Corp., Hopewell Junction, NY, USA ; K. Bernstein ; D. Heidel ; B. Klaasen
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The soft error rate in SOI devices is explored. Conventional SOI device soft error rate is compared to high mobility SOI and double gate SOI designs. We develop a theoretical understanding of the susceptibility of SOI devices to /spl alpha/-particle induced soft errors by means of simulations and measurements. Although high mobility devices will decrease soft error rate susceptibility, silicon thinning is shown to have a much larger impact. Double gate devices are shown to improve the soft error rate even further.

Published in:

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Date of Conference:

11-13 June 2002