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A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25 /spl mu/m CMOS

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5 Author(s)
J. Hyde ; Impinj Inc, Seattle, WA, USA ; T. Humes ; C. Diorio ; M. Thomas
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We describe a floating-gate trimmed, 14-bit, 250 Ms/s current-steered DAC fabricated in a 0.25 /spl mu/m CMOS logic process. We trim the static INL to /spl plusmn/0.3 LSB using analog charge stored on floating-gate pFETs. The DAC occupies 0.44 mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves 72 dB SFDR at 250 Ms/s.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002