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A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques

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9 Author(s)
Tang, S. ; Microprocessor Res., Intel Labs., Hillsboro, OR, USA ; Hsu, S. ; Ye, Y. ; Tschanz, J.
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Clock frequency of a multi-ported, 256/spl times/32b dynamic register file in a 100nm technology is improved by 50%, compared to the best dual-V/sub T/ (DVT) design, using LBSF and SFN leakage-tolerant circuit techniques for LBL and GBL. Total transistor width of the full LBSF design is the smallest.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002