A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques

Clock frequency of a multi-ported, 256/spl times/32b dynamic register file in a 100nm technology is improved by 50%, compared to the best dual-V/sub T/ (DVT) design, using LBSF and SFN leakage-tolerant circuit techniques for LBL and GBL. Total transistor width of the full LBSF design is the smallest.